The present invention relates to a process for forming a thin film transistor (TFT), and more particularly to a process for forming a thin film transistor used in a liquid crystal display (LCD).
Presently, the traditional picture tube display is gradually replaced because of the hung volume thereof and the radiation. The potential replacer is the liquid crystal display because the advantages of power-saving and easy carrying are achieved by using the liquid crystal display. Therefore, the liquid crystal display becomes the basic equipment for the notebook. Also, the liquid crystal display becomes the main stream of the table directive view plane display for applying to personal computers, video games, and monitors. Therefore, the liquid crystal display will be the leading product in the future.
Generally, most liquid crystal displays are manufactured by using the thin film transistors as driving devices, so that the output property of the thin film transistor affects the performance of the liquid crystal display mostly. Therefore, it is indeed an important issue to improve the process and the property of the thin film transistor.
FIGS. 1A-1E are schematic sectional views illustrating a method for forming a thin film transistor according to the prior art. As shown in FIG. 1A, a gate 11a is formed on a substrate 10 by two steps: (1) forming a conducting layer on the substrate 10, and (2) removing the conducting layer which is not located at the gate region by photolithography and etching for forming the gate 11a. Sequentially, a gate dielectric layer 12 and an amorphous silicon layer 13 are in order formed on the gate 11a and the amorphous silicon layer 13 is further formed into an amorphous silicon island as shown in FIG. 1B by photolithography and etching. Then, a doped amorphous silicon layer 15 and a metal layer 16 are in order formed on the gate dielectric layer 12, as is shown in FIG. 1C.
Referring to FIG. 1D, portions of the doped amorphous silicon layer 15 and the metal layer 16 are removed by photolithography and etching for forming a source 15a, a drain 15b, a source electrode 16a, and a drain electrode 16b, respectively. Sequentially, a passivation 17 is formed on portions of the gate dielectric layer 12 and the amorphous silicon island 13, the source electrode 16a, and the drain electrode 16b. The passivation 17 located on the drain electrode 16b is partially removed to form a contact window 19. Then, a transparent conducting later 18 is formed in the contact window 19 and on the passivation 17. After photolithography and etching, a pixel electrode 18a is formed as shown in FIG. 1E. Finally, after an annealing step for stabilizing the structure and modifying the crystallization and interface property thereof, the finished traditional structure of the thin film transistor is formed.
During the period of etching the doped amorphous silicon layer 15 and the metal layer 16, a portion of amorphous silicon layer 13 is also etched, which causes the amorphous silicon layer 13 becomes thinner. Thus, an etching stop layer whose composition is silicon nitride is generally formed on the amorphous silicon layer 13 by a plasma enhanced chemical vapor deposition (PECVD) for forming an etching stop thin film transistor. FIGS. 2A-2F illustrate a method for forming the etching stop thin film transistor according to the prior art. First of all, a gate 11a is formed on a substrate 10 as shown in FIG. 2A. Sequentially, a gate dielectric layer 12, an amorphous silicon layer 13, and an insulating layer 14 which is a silicon nitride are in order formed on the substrate 10 and the gate 11a (see FIG. 2B). Then, a portion of insulating layer 14 is removed by photolithography and etching for forming the etching stop layer 14a as shown in FIG. 2C. Sequentially, as shown in FIG. 2D, a doped amorphous silicon layer 15 and a metal layer 16 are in order formed on the amorphous silicon layer 13 and the etching stop layer 14a. 
FIG. 2E illustrates that portions of the amorphous silicon layer 13, the doped amorphous silicon layer 15, and the metal layer 16 are removed by photolithography and etching for forming a source 15a, a drain 15b, a source electrode 16a, and a drain electrode 16b. In this step, the amorphous silicon layer 13 is protected from etching owing to the etching stop layer 14a. Then, a passivation 17 is formed on portions of the gate dielectric layer 12, the etching stop layer 14a, the source electrode 16a, and the drain electrode 16b. Sequentially, the passivation 17 located on the drain electrode 16b is partially removed to form a contact window. Then, a transparent conducting layer is formed in the contact window and on the passivation 17. After photolithography and etching, a pixel electrode 18a is formed as shown in FIG. 2F. Finally, after an annealing step for stabilizing structure and modifying the crystallization and interface property thereof, a finished traditional structure of etching stop thin film transistor is formed.
However, the source 15a and the drain 15b are locates on the opposite side of the etching stop layer 14a, so that they can be a switch of the amorphous silicon layer 13 for generating the effect of a parasitic transistor. The effect of parasitic transistor results in a double hump phenomenon in the output property plot of the thin film transistor as shown in FIG. 3. FIG. 3 is a diagram illustrating the relation between the gate voltage and the drain current. When the gate of thin film transistor is applied a voltage, the current passing through the drain has a two-staged change in the linear region, or even a three-staged change called the triple hump phenomenon. Thus, it is impossible to clearly define the switch status, i.e. xe2x80x9conxe2x80x9d or xe2x80x9coffxe2x80x9d, of the thin film transistor, which is a serious defect of the thin film transistor as a driving device. In addition, while the interface properties of the etching stop layer 14a and those of the amorphous silicon layer 13 are not matched, or the device is damaged by plasma during etching the doped amorphous silicon layer 15 and the insulating layer 14, the problems of increasing the closing current, increasing the threshold voltage, decreasing the sub-threshold swing are occurred.
Currently, some methods have been developed for the thin film transistor to avoid the above undesired properties. One is that after forming the structure of the gate, the amorphous silicon layer, the source and the drain, the structure is treated by plasma before forming the passivation and the pixel electrode. Another is that after forming the amorphous silicon layer, the structure is treated by a first plasma treatment which infuses the decomposed ion into the amorphous silicon layer by a high energy plasma for filling the dangling bond. The other is similar with the previous one except after forming the passivation and the conducting electrode, the thin film transistor is treated by a H2O plasma. However, it is not only cost but also decreasing yield because of adding one or two steps of plasma treatment. In addition, the distribution of the plasma naturally cannot even, so it is hard to control in the large area process.
Besides the etching stop thin film transistor, the back channel etched thin film transistor is another general type. The process for producing the back channel etched thin film transistor is the same as that of the etching stop thin film transistor shown in FIGS. 1A-1E. After forming the source 15a and the drain 15b, the amorphous silicon layer 13 is exposed to the passivation 17. The exposed portion of the amorphous layer 13 will produce the interface defect because of the plasma erosion or the different silicon composition of the passivation 17. Thus, if the interface status is controlled improperly, the bad output property of the thin film transistor could be caused, and the photocurrent produced by illumination without applying a voltage to the gate could be increased.
Therefore, the purpose of the present invention is to develop a method to deal with the above situations encountered in the prior art.
It is therefore an object of the present invention to propose a process for forming a thin film transistor without a plasma treatment to improve the output property of the thin film transistor.
It is therefore another object of the present invention to propose a process for improving output property of a thin film transistor without a plasma treatment to reduce the cost and time of production.
According to the present invention, the process for forming a thin film transistor comprises steps of (a) forming a gate on a portion of a substrate, (b) forming a gate dielectric layer on the gate and the substrate, (c) forming a semiconductor layer on the gate dielectric layer, (d) defining a source and a drain on the semiconductor layer, (e) forming a passivation on the source, the drain, and the semiconductor layer, and (f) proceeding a thermal treatment under atmosphere of a specific assistant gas.
Certainly, the substrate can be a transparent substrate. The transparent substrate is preferably a glass substrate. The gate is one of a polysilicon and a metal. The gate dielectric layer is a silicon nitride layer.
Certainly, the semiconductor layer can be an amorphous silicon layer or an amorphous silicon layer forming thereon an etching stop layer. The etching stop layer can be a silicon nitride layer. The silicon nitride layer is formed by a plasma enhanced chemical vapor deposition.
Certainly, the source and the drain can be formed by one of an ion implantation and a plasma enhanced chemical vapor deposition.
Certainly, the passivation can be a silicon nitride layer.
Certainly, the specific assistant gas can be one selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof. When the specific assistant gas is hydrogen, the thermal treatment is performed at a temperature ranged from 200 to 300xc2x0 C. When the specific assistant gas is one selected from a gas mixture of steam and argon and a gas mixture of steam and nitrogen, and the steam has a volume ratio ranged from 20 to 100%, the thermal treatment is performed at a temperature ranged from 80 to 300xc2x0 C. When the specific assistant a gas mixture of hydrogen and nitrogen, and the hydrogen has a volume ratio ranged from 20 to 100%, the thermal treatment is performed a temperature ranged from 200 to 300xc2x0 C.
Certainly, the thermal treatment can have a treating time ranged from 10 minutes to 10 hours. The thermal treatment can be proceeded at atmosphere or at decompression ranged from 1 to 750 torr.
According to another aspect of the present invention, a process for improving a thin film transistor property, wherein the thin film transistor includes a substrate, a gate, a semiconductor layer, a source, a drain, and a passivation, comprises steps of providing a specific assistant gas which is selected from a group consisting of hydrogen, steam, inert gases, and gas mixtures thereof, and proceeding a thermal treatment with the thin film transistor at atmosphere of the assistant gas.
According to an additional aspect of the present invention, the process for producing a thin film transistor of a liquid crystal display includes steps of (a) forming a gate on a portion of a transparent substrate, (b) forming a gate dielectric layer on the gate and the substrate, (c) forming a semiconductor layer on the gate dielectric layer, (d) defining a source and a drain on the semiconductor layer, (e) forming a passivation on the source, the drain, and the semiconductor layer, (f) removing a portion of the passivation on the source and the drain for forming a contact window, (g) forming a conducting electrode in the contact window, and (h) proceeding a thermal treatment under atmosphere of a specific assistant gas.
Certainly, the step (f) can be preformed by a dry etching. The step (g) can further comprise steps of (g1) forming a conducting layer in the contact window and on the passivation, and (g2) removing the conducting layer on the passivation for forming the conducting electrode.
Certainly, the conducting layer can be a transparent conducting layer. The transparent conducting layer is preferably an indium-tin oxide layer.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which: